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CS42448 108 dB, 192 kHz 6-in, 8-out CODEC
FEATURES
Six 24-bit A/D, Eight 24-bit D/A Converters ADC Dynamic Range - 105 dB Differential - 102 dB Single-ended DAC Dynamic Range - 108 dB Differential - 105 dB Single-ended ADC/DAC THD+N - -98 dB Differential - -95 dB Single-ended Compatible with Industry-standard Time Division Multiplexed (TDM) Serial Interface System Sampling Rates up to 192 kHz Programmable ADC High-pass Filter for DC Offset Calibration Logarithmic Digital Volume Control IC & SPITM Host Control Port Supports Logic Levels Between 5 V and 1.8 V Popguard(R) Technology
GENERAL DESCRIPTION
The CS42448 CODEC provides six multi-bit analog-to-digital and eight multi-bit digital-to-analog Delta-sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a 64-pin LQFP package. Six fully differential, or single-ended, inputs are available on stereo ADC1, ADC2, and ADC3. When operating in Singleended Mode, an internal MUX before ADC3 allows selection from up to four single-ended inputs. Digital volume control is provided for each ADC channel, with selectable overflow detection. All eight DAC channels provide digital volume control and can operate with differential or single-ended outputs. An auxiliary serial input is available for an additional two channels of PCM data. The CS42448 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and automotive audio systems.
ORDERING INFORMATION
See page 67.
Control Port & Serial Audio Port Supply = 1.8 V to 5 V
Digital Supply = 3.3 V to 5 V
Analog Supply = 3.3 V to 5 V
Level Translator
I2C/SPI Software Mode Control Data
Register Configuration ADC Overflow & Clock Error Interrupt
Internal Voltage Reference External Mute Control Mute Control
Interrupt Reset
PCM or TDM Serial Interface
Serial Audio Input Level Translator Auxilliary Serial Audio Input Input Master Clock Serial Audio Output
Volume Controls
Digital Filters
Modulators
Multibit DAC1-4 and Analog Filters
8 8
Differential or Single-Ended Outputs
High Pass Filter
Digital Filters
Multibit Oversampling ADC1&2 Multibit Oversampling ADC3
4:2*
4 4
High Pass Filter
Digital Filters
Differential or Single-Ended Analog Inputs
2 2
*Optional MUX allows selection from up to 4 single-ended inputs.
Preliminary Product Information
Cirrus Logic, Inc. http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
FEB `05 DS648PP2
TABLE OF CONTENTS
1 PIN DESCRIPTION .................................................................................................................... 6 1.1 Digital I/O Pin Characteristics ............................................................................................ 8 2 TYPICAL CONNECTION DIAGRAM ......................................................................................... 9 3 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 10 SPECIFIED OPERATING CONDITIONS ............................................................................... 10 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10 ANALOG INPUT CHARACTERISTICS (CS42448-CQZ) ....................................................... 11 ANALOG INPUT CHARACTERISTICS (CS42448-DQZ) ....................................................... 12 ADC DIGITAL FILTER CHARACTERISTICS ......................................................................... 13 ANALOG OUTPUT CHARACTERISTICS (CS42448-CQZ) ................................................... 14 ANALOG OUTPUT CHARACTERISTICS (CS42448-DQZ) ................................................... 16 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ................ 18 SWITCHING SPECIFICATIONS - ADC/DAC PORT .............................................................. 19 SWITCHING CHARACTERISTICS - AUX PORT................................................................... 21 SWITCHING SPECIFICATIONS - CONTROL PORT - IC MODE......................................... 22 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................... 23 DC ELECTRICAL CHARACTERISTICS................................................................................. 24 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ....................................... 24 4 APPLICATIONS ....................................................................................................................... 25 4.1 Overview .......................................................................................................................... 25 4.2 Analog Inputs ................................................................................................................... 25 4.2.1 Line Level Inputs ................................................................................................. 25 4.2.2 ADC3 Analog Input ............................................................................................. 26 4.2.3 High Pass Filter and DC Offset Calibration ......................................................... 27 4.3 Analog Outputs ................................................................................................................ 27 4.3.1 Initialization ......................................................................................................... 27 4.3.2 Output Transient Control ..................................................................................... 27 4.3.3 Popguard(R) .......................................................................................................... 29 4.3.4 Mute Control ........................................................................................................ 29 4.3.5 Line-level Outputs and Filtering .......................................................................... 29 4.3.6 Digital Volume Control ........................................................................................ 30 4.3.7 De-Emphasis Filter .............................................................................................. 30 4.4 System Clocking .............................................................................................................. 31 4.5 CODEC Digital Interface Formats .................................................................................... 31 4.5.1 IS ........................................................................................................................ 33 4.5.2 Left-Justified ........................................................................................................ 33 4.5.3 Right Justified ..................................................................................................... 33 4.5.4 OLM #1 ............................................................................................................... 33 4.5.5 OLM #2 ............................................................................................................... 34 4.5.6 TDM .................................................................................................................... 34 4.5.7 I/O Channel Allocation ........................................................................................ 35 4.6 AUX Port Digital Interface Formats .................................................................................. 36 4.6.1 IS ........................................................................................................................ 36 4.6.2 Left Justified ........................................................................................................ 36 4.7 Control Port Description and Timing ................................................................................ 37 4.7.1 SPI Mode ............................................................................................................ 37 4.7.2 I2C Mode ............................................................................................................. 38 4.8 Interrupts .......................................................................................................................... 39 4.9 Recommended Power-up Sequence ............................................................................... 39 4.10 Reset and Power-up ..................................................................................................... 39 4.11 Power Supply, Grounding, and PCB layout ................................................................... 40
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5 REGISTER QUICK REFERENCE ........................................................................................... 41 6 REGISTER DESCRIPTION ..................................................................................................... 43 6.1 Memory Address Pointer (MAP) ....................................................................................... 43 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) ............................................ 43 6.3 Power Control (address 02h)............................................................................................ 44 6.4 Functional Mode (address 03h)........................................................................................ 45 6.5 Interface Formats (address 04h) ...................................................................................... 46 6.6 ADC Control & DAC De-emphasis (address 05h) ............................................................ 48 6.7 Transition Control (address 06h) ...................................................................................... 49 6.8 DAC Channel Mute (address 07h) ................................................................................... 51 6.9 AOUTX Volume Control (addresses 08h- 0Fh) ............................................................ 51 6.10 DAC Channel Invert (address 10h) ................................................................................ 52 6.11 AINX Volume Control (address 11h-16h) ....................................................................... 52 6.12 ADC Channel Invert (address 17h) ................................................................................ 52 6.13 Status Control (address 18h).......................................................................................... 53 6.14 Status (address 19h) (Read Only)................................................................................. 53 6.15 Status Mask (address 1Ah) ............................................................................................ 54 6.16 MUTEC Pin Control (address 1Bh) ................................................................................ 54 7 APPENDIX A: EXTERNAL FILTERS ...................................................................................... 55 7.1 ADC Input Filter ............................................................................................................... 55 7.1.1 Passive Input Filter ............................................................................................. 56 7.1.2 Passive Input Filter w/Attenuation ....................................................................... 56 7.2 DAC Output Filter ............................................................................................................ 58 8 APPENDIX B: ADC FILTER PLOTS ....................................................................................... 59 9 APPENDIX C: DAC FILTER PLOTS ....................................................................................... 61 10 PARAMETER DEFINITIONS ................................................................................................. 63 11 REFERENCES ....................................................................................................................... 64 12 PACKAGE INFORMATION ................................................................................................... 65 12.1 Thermal Characteristics ................................................................................................ 65 13 ORDERING INFORMATION ................................................................................................. 66 14 REVISION HISTORY ............................................................................................................. 67
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LIST OF FIGURES
Figure 1. Typical Connection Diagram ............................................................................................ 9 Figure 2. Output Test Load ........................................................................................................... 17 Figure 3. Maximum Loading.......................................................................................................... 17 Figure 4. Serial Audio Interface Slave Mode Timing ..................................................................... 19 Figure 5. TDM Serial Audio Interface Timing ................................................................................ 19 Figure 6. Serial Audio Interface Master Mode Timing ................................................................... 20 Figure 7. Serial Audio Interface Slave Mode Timing ..................................................................... 21 Figure 8. Control Port Timing - IC Format.................................................................................... 22 Figure 9. Control Port Timing - SPI Format................................................................................... 23 Figure 10. Full-Scale Input ............................................................................................................ 26 Figure 11. ADC3 Input Topology................................................................................................... 26 Figure 12. Audio Output Initialization Flow Chart .......................................................................... 28 Figure 13. Full-Scale Output ......................................................................................................... 30 Figure 14. De-Emphasis Curve ..................................................................................................... 30 Figure 15. IS Format .................................................................................................................... 33 Figure 16. Left Justified Format..................................................................................................... 33 Figure 17. Right Justified Format .................................................................................................. 33 Figure 18. One Line Mode #1 Format ........................................................................................... 33 Figure 19. One Line Mode #2 Format ........................................................................................... 34 Figure 20. TDM Format ................................................................................................................. 34 Figure 21. AUX IS Format............................................................................................................ 36 Figure 22. AUX Left Justified Format ............................................................................................ 36 Figure 23. Control Port Timing in SPI Mode.................................................................................. 37 Figure 24. Control Port Timing, IC Write ...................................................................................... 38 Figure 25. Control Port Timing, IC Read...................................................................................... 38 Figure 26. Single to Differential Active Input Filter ........................................................................ 55 Figure 27. Single-Ended Active Input Filter................................................................................... 55 Figure 28. Passive Input Filter....................................................................................................... 56 Figure 29. Passive Input Filter w/Attenuation................................................................................ 57 Figure 30. Active Analog Output Filter .......................................................................................... 58 Figure 31. Passive Analog Output Filter........................................................................................ 58 Figure 32. SSM Stopband Rejection ............................................................................................. 59 Figure 33. SSM Transition Band ................................................................................................... 59 Figure 34. SSM Transition Band (Detail)....................................................................................... 59 Figure 35. SSM Passband Ripple ................................................................................................. 59 Figure 36. DSM Stopband Rejection............................................................................................. 59 Figure 37. DSM Transition Band ................................................................................................... 59 Figure 38. DSM Transition Band (Detail) ...................................................................................... 60 Figure 39. DSM Passband Ripple ................................................................................................. 60 Figure 40. QSM Stopband Rejection............................................................................................. 60 Figure 41. QSM Transition Band................................................................................................... 60 Figure 42. QSM Transition Band (Detail) ...................................................................................... 60 Figure 43. QSM Passband Ripple................................................................................................. 60 Figure 44. SSM Stopband Rejection ............................................................................................. 61 Figure 45. SSM Transition Band ................................................................................................... 61 Figure 46. SSM Transition Band (detail) ....................................................................................... 61 Figure 47. SSM Passband Ripple ................................................................................................. 61 Figure 48. DSM Stopband Rejection............................................................................................. 61 Figure 49. DSM Transition Band ................................................................................................... 61 Figure 50. DSM Transition Band (detail) ....................................................................................... 62 Figure 51. DSM Passband Ripple ................................................................................................. 62
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Figure 52. QSM Stopband Rejection ............................................................................................ 62 Figure 53. QSM Transition Band................................................................................................... 62 Figure 54. QSM Transition Band (detail)....................................................................................... 62 Figure 55. QSM Passband Ripple................................................................................................. 62
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LIST OF TABLES
Table 1. I/O Power Rails ........................................................................................................................ 8 Table 2. Single-Speed Mode Common Frequencies ........................................................................... 31 Table 3. Double-Speed Mode Common Frequencies ......................................................................... 31 Table 4. Quad-Speed Mode Common Frequencies ............................................................................ 31 Table 5. IS, LJ, RJ Clock Ratios ......................................................................................................... 32 Table 6. OLM#1 Clock Ratios .............................................................................................................. 32 Table 7. OLM#2 Clock Ratios .............................................................................................................. 32 Table 8. TDM Clock Ratios .................................................................................................................. 32 Table 9. Serial Audio Interface Channel Allocations............................................................................ 35 Table 10. MCLK Frequency Settings for IS, Left and Right Justified Interface Formats .................... 45 Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats ........................................... 46 Table 12. DAC Digital Interface Formats ............................................................................................. 47 Table 13. ADC Digital Interface Formats ............................................................................................. 47 Table 14. Example AOUT Volume Settings......................................................................................... 51 Table 15. Example AIN Volume Settings............................................................................................. 52 Table 16. Revision History ................................................................................................................... 67
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1 PIN DESCRIPTION
AIN6+/AIN6A SDA/CDOUT AIN5+/AIN5A AIN6-/AIN6B AIN5-/AIN5B FILT+_ADC FILT+_DAC SCL/CCLK
DGND
AGND
AIN4+
AIN3+
AIN4-
INT
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AD0/CS AD1/CDIN RST VLC ADC_LRCK VD DGND VLS ADC_SCLK MCLK ADC_SDOUT3 ADC_SDOUT2 ADC_SDOUT1 DAC_SDIN4 DAC_SDIN3 DAC_SDIN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DAC_SDIN1 DAC_LRCK DAC_SCLK AOUT1+ AOUT2+ AOUT3+ AUX_LRCK AUX_SCLK AUX_SDIN AOUT4+ DGND VD AOUT1AOUT2AOUT3AOUT448 47 46 45 44 43 42 AIN2+ AIN2AIN1+ AIN1VA VQ AGND AOUT8AOUT8+ AOUT7+ AOUT7AOUT6AOUT6+ MUTEC AOUT5+ AOUT5-
CS42448
VA
AIN341 40 39 38 37 36 35 34 33
Pin Name
AD0/CS AD1/CDIN RST VLC ADC_LRCK
#
1 2 3 4 5
Pin Description
Address Bit [0]/ Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select the chip in SPI mode. Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I2C Mode. Input for SPI data. Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. Control Port Power (Input) - Determines the required signal level for the control port. See "Digital I/O Pin Characteristics" on page 9. ADC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the ADC serial audio data line. Signals the start of a new TDM frame in the TDM digital interface format.
VD DGND VLS ADC_SCLK MCLK ADC_SDOUT1 ADC_SDOUT2 ADC_SDOUT3
6, 24 Digital Power (Input) - Positive terminal of the power supply for the digital section. 7, 23, Digital Ground (Input) - Ground terminal of the power supply for the digital section. 62 8 9 10 13 12 11 Serial Port Interface Power (Input) - Determines the required signal level for the serial interfaces. See "Digital I/O Pin Characteristics" on page 9. ADC Serial Clock (Input/Output) - Serial clock for the ADC serial audio interface. Input frequency must be 256xFs in the TDM digital interface format. Master Clock (Input) - Clock source for the Delta-Sigma modulators and digital filters. Serial Audio Data Output (Output) - Outputs for two's complement serial audio data.
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DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 DAC_SCLK DAC_LRCK
17 16 15 14 18 19
DAC Serial Audio Data Input (Input) - Input for two's complement serial audio data.
DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface. Input frequency must be 256xFs in the TDM digital interface format. DAC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the DAC serial audio data line. Signals the start of a new TDM frame in the TDM digital interface format. Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. Derived from the ADC serial port and equals Fs. Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. Auxiliary Serial Input (Input) - Provides an additional serial input for two's complement serial audio data. Used only in the TDM digital interface format.
AUX_LRCK AUX_SCLK AUX_SDIN AOUT1 +,AOUT2 +,AOUT3 +,AOUT4 +,AOUT5 +,AOUT6 +,AGND VQ VA AIN1 +,AIN2 +,AIN3 +,AIN4 +,AIN5 +,AIN6 +,AIN5 A,B AIN6 A,B
20 21 22
26,25 Differential Analog Output (Output) - The full-scale analog output level is specified in the Analog 27,28 Characteristics table. Each leg of the differential outputs may also be used single-ended. 30,29 31,32 34,33 36,37 42,56 Analog Ground (Input) 43 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
44,53 Analog Power (Input) - Positive power supply for the analog section. See "Digital I/O Pin Characteristics" on page 9. 46,45 Differential Analog Input (Input) - Signals are presented differentially or single-ended to the 48,47 Delta-Sigma modulators. The full-scale input level is specified in the Analog Characteristics speci50,49 fication table. See below for a description of AIN5-AIN6 in Single-Ended Mode. 52,51 58,57 60,59 58,57 Single-Ended Analog Input (Input) - When stereo ADC3 is in Single-Ended Mode, an internal 60,59 analog mux allows selection between 2 channels for both analog inputs AIN5 and AIN6 (see section 4.2.2 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics table. 35 54 55 61 63 64 Mute Control (Output) - Used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits of the DAC. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits of the ADC. Interrupt (Output) - Signals either an ADC overflow condition has occurred in one or more of the ADC inputs, or a clocking error has occurred in the DAC/ADC as specified in the Interrupt register. Serial Control Port Clock (Input) - Serial clock for the control port interface. Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Output for SPI data.
MUTEC FILT+_DAC FILT+_ADC INT SCL/CCLK SDA/CDOUT
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1.1
Digital I/O Pin Characteristics
Various pins on the CS42448 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings.
Power Rail
VLC
Pin Name
RST SCL/CCLK SDA/CDOUT
I/O
Driver 1.8 V - 5.0 V, CMOS/Open Drain 1.8 V - 5.0 V, CMOS/Open Drain 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 3.3 V - 5.0 V, CMOS
Table 1. I/O Power Rails
Receiver 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS, with Hysteresis 1.8 V - 5.0 V, CMOS, with Hysteresis 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS -
VLS
VA
Input Input Input/ Output AD0/CS Input AD1/CDIN Input INT Output MCLK Input ADC_LRCK Input/ Output ADC_SCLK Input/ Output ADC_SDOUT1-3 Input/ (ADC3_SINGLE) Output DAC_LRCK Input/ Output DAC_SCLK Input/ Output DAC_SDIN1-4 Input AUX_LRCK Output AUX_SCLK Output AUX_SDIN Input MUTEC Output
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2 TYPICAL CONNECTION DIAGRAM
+3.3 V to +5 V 10 F + 0.1 F 0.01 F 0.01 F 0.1 F + +3.3 V to +5 V 10 F
0.1 F
0.01 F
6 24 53 44
0.01 F
0.1 F
VD
VD
VA
VA
AOUT1+ AOUT1AOUT2+ AOUT28
26 25 27 28 30 29 34 33 34 33 36 37 39 38 40 41
Analog Output Filter 2 Analog Output Filter2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2
VLS
AOUT3+ AOUT3AOUT4+ AOUT4-
0.01 F
22
CS5341 A/D Converter
21 20
AUX_SDIN AUX_SCLK AUX_LRCK
AOUT5+ AOUT5AOUT6+ AOUT6AOUT7+ AOUT7-
CS8416 Receiver S/PDIF
optional connection
OSC RMCK
AOUT8+ AOUT8-
MUTEC
10 9
35
Mute Drive (optional)
MCLK ADC_SCLK ADC_LRCK ADC_SDOUT1 ADC_SDOUT2 ADC_SDOUT3 DAC_SCLK DAC_LRCK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 INT RST SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3AIN4+ AIN4AIN5+/AIN5A
46 45 48 47 50 49 52 51
+1.8 V to +5.0 V
5 13 12 11
Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1
Analog Input 1
Analog Input 2
Digital Audio Processor
18 19 17 16 15 14
Analog Input 3
Analog Input 4
58 57 60 59
61 3
AIN5-/AIN5B AIN6+/AIN6A AIN6-/AIN6B
Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1 Input Filter 1
Analog Input 5
MicroController
63 64 2 1
Analog Input 6
Analog Input 5A Analog Input 5B Analog Input 6A Analog Input 6B
** 2 k +1.8 V to +5 V
** Resistors are required for I2C control port operation
**
2 k
4
VLC
0.1 F VQ FILT+_ADC FILT+_DAC
43 55 54
+ DGND DGND DGND
7 23 62
+ 100 F 0.1 F 22 F 0.1 F
+ 4.7 F
AGND
56
AGND
42
0.1 F
Connect DGND and AGND near CODEC
1. See the ADC Input Filter section in the Appendix. 2. See the DAC Output Filter section in the Appendix.
Figure 1. Typical Connection Diagram
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3 CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25 C.)
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.) Parameters DC Power Supply Analog
(Note 1)
Symbol 3.3 V 5.0 V 3.3 V 5.0 V 1.8 V (Note 2) 2.5 V 3.3 V 5.0 V 1.8 V 2.5 V 3.3 V 5.0 V -CQZ -DQZ VA VD VLS
Min 3.14 4.75 3.14 4.75 1.71 2.37 3.14 4.75 1.71 2.37 3.14 4.75 -10 -40
Typ 3.3 5 3.3 5 1.8 2.5 3.3 5 1.8 2.5 3.3 5 -
Max 3.47 5.25 3.47 5.25 1.89 2.63 3.47 5.25 1.89 2.63 3.47 5.25 +70 +85
Units V V V V V V V V V V V V C C
Digital Serial Audio Interface
Control Port Interface
VLC
Ambient Temperature Commercial Automotive
TA
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Analog Digital Serial Port Interface Control Port Interface
(Note 3) (Note 4)
Input Current Analog Input Voltage Digital Input Voltage
(Note 4)
Serial Port Interface Control Port Interface CS42448-CQZ CS42448-DQZ
Ambient Operating Temperature (power applied) Storage Temperature
Symbol VA VD VLS VLC Iin VIN VIND-S VIND-C TA Tstg
Min -0.3 -0.3 -0.3 -0.3 AGND-0.7 -0.3 -0.3 -20 -50 -65
Max 6.0 6.0 6.0 6.0 10 VA+0.7 VLS+ 0.4 VLC+ 0.4 +85 +95 +150
Units V V V V mA V V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Analog input/output performance will slightly degrade at VA = 3.3 V. 2. The ADC_SDOUT may not meet timing requirements in TDM, Double-Speed Mode. 3. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 4. The maximum over/under voltage is limited by the input current. DS648PP2 11
ANALOG INPUT CHARACTERISTICS (CS42448-CQZ)
(Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz through the active input filter on page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.)
Differential Parameter Single Speed Mode Dynamic Range Min 99 96 99 96 99 96 Typ 105 102 -98 -82 -42 105 102 99 -98 -82 -42 -90 105 102 99 -98 -82 -42 -87 90 90 0.1 100 Max -92 -92 -92 Min 96 93 96 93 96 93 Fs=48 kHz A-weighted unweighted Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB Fs=96 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB Fs=192 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB
Single-Ended Typ 102 99 -95 -79 -39 102 99 96 -95 -79 -39 -90 102 99 96 -95 -79 -39 -87 90 90 0.1 100 Max -89 -89 -89 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/C Vpp k k dB
Double Speed Mode Dynamic Range
Quad Speed Mode Dynamic Range
All Speed Modes ADC1-3 Interchannel Isolation ADC3 MUX Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Input Full-scale Input Voltage Differential Input Impedance (Note 6) Single-Ended Input Impedance (Note 7) Common Mode Rejection Ratio (CMRR)
-
-
1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59*VA 18 18 82 -
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ANALOG INPUT CHARACTERISTICS (CS42448-DQZ)
(Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz through the active input filter on page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.)
Differential Parameter Single Speed Mode Dynamic Range Min 97 94 97 94 97 94 Typ 105 102 -98 -82 -42 105 102 99 -98 -82 -42 -87 105 102 99 -98 -82 -42 -87 90 85 0.1 100 Max -90 -90 -90 Min 94 91 94 91 94 91 Fs=48 kHz A-weighted unweighted Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB Fs=96 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB Fs=192 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB
Single-Ended Typ 102 99 -95 -79 -39 102 99 96 -95 -79 -39 -87 102 99 96 -95 -79 -39 -87 90 85 0.1 100 Max -87 -87 -87 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/C Vpp k k dB
Double Speed Mode Dynamic Range
Quad Speed Mode Dynamic Range
All Speed Modes ADC1-3 Interchannel Isolation ADC3 MUX Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Input Full-scale Input Voltage Differential Input Impedance (Note 6) Single-Ended Input Impedance (Note 7) Common Mode Rejection Ratio (CMRR)
1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA 18 18 82 -
Notes: 5. Referred to the typical full-scale voltage. 6. Measured between AINx+ and AINx-. 7. Measured between AINxx and AGND.
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ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 8, 9) Single Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay Double Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay Quad Speed Mode (Note 9) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Notes: 8. Filter response is guaranteed by design. 9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 32 to 43) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. -3.0 dB -0.13 dB @ 20 Hz 1 20 10 105/Fs 0 0 Hz Hz Deg dB s to -0.1 dB corner 0 0.5000 60 5/Fs 0.2604 0.16 Fs dB Fs dB s to -0.1 dB corner 0 0.5604 69 9/Fs 0.4896 0.16 Fs dB Fs dB s to -0.1 dB corner 0 0.5688 70 12/Fs 0.4896 0.08 Fs dB Fs dB s Min Typ Max Unit
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ANALOG OUTPUT CHARACTERISTICS (CS42448-CQZ)
(Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 11); Single-ended test load: RL = 3 k, CL = 10 pF.) Differential Typ Single-Ended Typ Max
Parameter Single-Speed Mode Fs = 48 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Double-Speed Mode Fs = 96 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Quad-Speed Mode Fs = 192 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB
Min
Max
Min
Unit
102 99 -
108 105 99 96 -98 -85 -45 -93 -76 -36
-92 -
99 96 -
105 102 96 93 -95 -82 -42 -90 -73 -33
-89 -
dB dB dB dB dB dB dB dB dB dB
102 99 -
108 105 99 96 -98 -85 -45 -93 -76 -36
-92 -
99 96 -
105 102 96 93 -95 -82 -42 -90 -73 -33
-89 -
dB dB dB dB dB dB dB dB dB dB
102 99 -
108 105 99 96 -98 -85 -45 -93 -76 -36
-92 -
99 96 -
105 102 96 93 -95 -82 -42 -90 -73 -33
-89 -
dB dB dB dB dB dB dB dB dB dB
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All Speed Modes Interchannel Isolation (1 kHz) Analog Output Full Scale Output 1.235*VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin (Note 10)
100
-
-
100
-
dB
1.300*VA 1.365*VA 0.618*VA 0.650*VA 0.683*VA Vpp 0.1 0.25 0.1 0.25 dB 100 100 ppm/C 100 100 10 10 A 100 3 100 k pF
AC-Load Resistance (RL) Load Capacitance (CL)
(Note 12) (Note 12)
3 -
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ANALOG OUTPUT CHARACTERISTICS (CS42448-DQZ)
(Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V, VA = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 11); Single-ended test load: RL = 3 k, CL = 10 pF.) Differential Typ Single-Ended Typ Max
Parameter Single-Speed Mode Fs = 48 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Double-Speed Mode Fs = 96 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Quad-Speed Mode Fs = 192 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB
Min
Max
Min
Unit
100 97 -
108 105 99 96 -98 -85 -45 -93 -76 -36
-90 -
97 94 -
105 102 96 93 -95 -82 -42 -90 -73 -33
-87 -
dB dB dB dB dB dB dB dB dB dB
100 97 -
108 105 99 96 -98 -85 -45 -93 -76 -36
-90 -
97 94 -
105 102 96 93 -95 -82 -42 -90 -73 -33
-87 -
dB dB dB dB dB dB dB dB dB dB
100 97 -
108 105 99 96 -98 -85 -45 -93 -76 -36
-90 -
97 94 -
105 102 96 93 -95 -82 -42 -90 -73 -33
-87 -
dB dB dB dB dB dB dB dB dB dB
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All Speed Modes Interchannel Isolation (1 kHz) Analog Output Full Scale Output 1.210*VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin (Note 10)
100
-
-
100
-
dB
1.300*VA 1.392*VA 0.605*VA 0.650*VA 0.696*VA Vpp 0.1 0.25 0.1 0.25 dB 100 100 ppm/C 100 100 10 10 A 100 3 100 k pF
AC-Load Resistance (RL) Load Capacitance (CL)
(Note 12) (Note 12)
3 -
Notes: 10. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC blocking capacitors. 11. One-half LSB of triangular PDF dither is added to data. 12. Guaranteed by design. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See Appendix A for a recommended output filter.
125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region
DAC1-4 AOUTxx
3.3 F +
Analog Output
RL CL
AGND
2.5 3
5 10 15 20
Resistive Load -- RL (k )
Figure 2. Output Test Load
Figure 3. Maximum Loading
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COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 8, 13) Single Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 15) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.1 dB corner to -3 dB corner (Note 14) to -0.05 dB corner to -3 dB corner 0 0 -0.2 0.5465 50 0 0 -0.2 0.5770 (Note 14) 55 to -0.1 dB corner to -3 dB corner 0 0 -0.2 0.7 (Note 14) 51 10/Fs 5/Fs 2.5/Fs 0.4780 0.4996 +0.08 Fs Fs dB Fs dB s Min Typ Max Unit
+1.5/+0 dB +0.05/-0.25 dB -0.2/-0.4 dB 0.4650 0.4982 +0.7 0.397 0.476 +0.05 Fs Fs dB Fs dB s Fs Fs dB Fs dB s
Double Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay
Notes: 13. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 44 to 55) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 14. Single and Double Speed Mode Measurement Bandwidth is from Stopband to 3 Fs. Quad Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs. 15. De-emphasis is only available in Single Speed Mode.
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SWITCHING SPECIFICATIONS - ADC/DAC PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS,
ADC_SDOUT CLOAD = 15 pF.) Parameters (Note 20) Slave Mode RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate (LRCK)
(Note 17) (Note 16)
Symbol
Min 1 0.512 45
Max 50 55 50 100 200 55 55 35 -
Units ms MHz % kHz kHz kHz % % ns ns ns ns ns ns ns ns ns ns
Single-Speed Mode Double-Speed Mode (Note 18) Quad-Speed Mode (Note 19)
Fs Fs Fs
4 50 100 45 45
LRCK Duty Cycle SCLK Duty Cycle SCLK High Time SCLK Low Time LRCK Rising Edge to SCLK Rising Edge SCLK Rising Edge to LRCK Falling Edge SCLK Falling Edge to ADC_SDOUT Output Valid DAC_SDIN Setup Time Before SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge ADC_SDOUT Hold Time After SCLK Rising Edge ADC_SDOUT Valid Before SCLK Rising Edge tsckh tsckl tfss tlcks tfsh tdpd tds tdh tdh1 tdh2 tdval
8 8 5 16 3 5 5 10 15
LRCK
LRCK
(input)
tlcks
t sckh
tsckl
SCLK
(input)
tfss
tfsh
tsckh
tsckl
SCLK
tds
DAC_SDINx
t dh
MSB MSB-1
DAC_SDIN1
tds
tdh1
MSB MSB-1
tdpd
ADC_SDOUTx
MSB MSB-1
ADC_SDOUT1
MSB
tdh2
tdval
MSB-1
Figure 4. Serial Audio Interface Slave Mode Timing
Figure 5. TDM Serial Audio Interface Timing
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Parameters (Note 20) Master Mode Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Edge to SCLK Rising Edge SCLK Falling Edge to ADC_SDOUT Output Valid DAC_SDIN Setup Time Before SCLK Rising Edge DAC_SDIN Hold Time After SCLK Rising Edge All Speed Modes
Symbol Fs
Min 45 45
Max MCLK / 256 55 64 x Fs 55 5 35 -
Units kHz % MHz % ns ns ns ns
tlcks tdpd tds tdh1
3 5
Notes: 16. After powering up the CS42448, RST should be held low after the power supplies and clocks are settled. 17. See Table 10 on page 46 and Table 11 on page 47 for suggested MCLK frequencies. 18. When operating in TDM interface format, VLS is limited to nominal 2.5 V to 5.0 V operation only. 19. ADC - IS, Left-Justified, Right-Justified interface formats only. DAC - IS, Left-Justified, Right-Justified and Time Division Multiplexed interface formats only. 20. "LRCK" and "SCLK" shall refer to the ADC and DAC left/right clock and serial clock, respectively.
LRCK
tlcks
SCLK
tds
DAC_SDINx
tdh
MSB MSB-1
tdpd
ADC_SDOUTx
MSB MSB-1
Figure 6. Serial Audio Interface Master Mode Timing
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SWITCHING CHARACTERISTICS - AUX PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS.)
Parameters Master Mode Output Sample Rate (AUX_LRCK) AUX_SCLK Frequency AUX_SCLK Duty Cycle AUX_LRCK Edge to SCLK Rising Edge AUX_SDIN Setup Time Before SCLK Rising Edge AUX_SDIN Hold Time After SCLK Rising Edge tlcks tds tdh All Speed Modes Fs 45 3 5 ADC_LRCK 64*ADC_LRCK 55 5 kHz kHz % ns ns ns Symbol Min Max Units
AUX_LRCK
tlcks
tsckh
tsckl
AUX_SCLK
tds
AUX_SDIN
tdh
MSB MSB-1
Figure 7. Serial Audio Interface Slave Mode Timing
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SWITCHING SPECIFICATIONS - CONTROL PORT - IC MODE
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling
(Note 22) (Note 22) (Note 21)
Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack
Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300
Max 100 1 300 1000
Unit kHz ns s s s s s s ns s ns s ns
Notes: 21. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 22. Guaranteed by design.
RST t Stop irs Start R e p e a te d Sta rt t rd t fd Stop
SDA t buf t hdst t high t hdst t fc t susp
SCL t t t sud t ack t sust t rc
lo w
hdd
Figure 8. Control Port Timing - IC Format
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SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF) Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN
(Note 24) (Note 24) (Note 23)
Symbol fsck tsrs tcss tcsh tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2
Min 0 20 20 1.0 66 66 40 15 -
Max 6.0 50 25 25 100 100
Units MHz ns ns s ns ns ns ns ns ns ns ns ns
Notes: 23. Data must be held for sufficient time to bridge the transition time of CCLK. 24. For fsck <1 MHz.
RST
tsrs
CS
tcsh tcss tsch tscl tr2
CCLK
tf2 tdsu tdh
CDIN
tpd
MSB
CDOUT
MSB
Figure 9. Control Port Timing - SPI Format
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DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.) Parameters Normal Operation (Note 25) Power Supply Current VA = 5.0 V VLS = VLC = VD = 3.3 V
(Note 26)
Symbol IA IDT
Min -
Typ 80 60.6 600 60 40 1.25 0.5*VA 23 VA VA
Max 850 10 -
Units mA mA mW dB dB mW V
Power Dissipation Power Supply Rejection Ratio
(Note 27)
All Supplies = 5 V 1 kHz 60 Hz All Supplies = VA = 5 V PSRR
-
Power-down Mode (Note 28) Power Dissipation VQ Characteristics Nominal Voltage Output Impedance DC current source/sink (Note 29) FILT+_ADC Nominal Voltage FILT+_DAC Nominal Voltage
k
A V V
Notes: 25. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input to the DAC and AUX port, and a 1 kHz, -1 dB analog input to the ADC port sampled at the highest Fs for each speed mode. DAC outputs are open, unless otherwise specified. 26. IDT measured with no external loading on pin 64 (SDA). 27. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also increase the PSRR. 28. Power Down Mode is defined as RST = LO with all clocks and data lines held static and no analog input. 29. Guaranteed by design. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through the electrolytic de-coupling capacitors.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 30) High-Level Output Voltage at Io=2 mA Serial Port Control Port MUTEC Serial Port Control Port MUTEC Serial Port Control Port Serial Port Control Port Symbol VOH Min VLS-1.0 VLC-1.0 VA-1.0 0.7xVLS 0.7xVLC Typ 3 Max 0.4 0.4 0.4 0.2xVLS 0.2xVLC 10 10 Units V V V V V V V V V V A pF mA
Low-Level Output Voltage at Io=2 mA
VOL
High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance (Note 22) MUTEC Drive Current
VIH VIL Iin
Notes: 30. See "Digital I/O Pin Characteristics" on page 9 for serial and control port power rails.
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4 APPLICATIONS 4.1 Overview
The CS42448 is a highly integrated mixed signal 24-bit audio CODEC comprised of 6 analog-to-digital converters (ADC), implemented using multi-bit delta-sigma techniques, and 8 digital-to-analog converters (DAC) also implemented using multi-bit delta-sigma techniques. Other functions integrated within the CODEC include independent digital volume controls for each DAC, digital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC highpass filters, an on-chip voltage reference and Popguard(R) technology that minimizes the effects of output transients on power-up and power-down. All serial data is transmitted through two independent serial ports: the DAC serial port and the ADC serial port. Each serial port can be configured independently to operate at different sample and clock rates, but both must run synchronous to each other. The serial audio interface ports allow up to 8 DAC channels and 8 ADC channels in a Time-Division Multiplexed (TDM) interface format. In the One-Line Mode (OLM) interface format, the CS42448 will allow up to 6 ADC channels on one data line and up to 8 DAC channels on 2 data lines. The CS42448 features an Auxiliary Port used to accommodate an additional two channels of PCM data on the ADC_SDOUT data line in the TDM digital interface format. See "AUX Port Digital Interface Formats" on page 37 for details. The CS42448 operates in one of three oversampling modes based on the input sample rate. When operating the CODEC as a slave, mode selection is determined automatically based on the MCLK frequency setting. When operating as a master, mode selection is determined by the ADC and DAC FM bits in register "Functional Mode (address 03h)" on page 46. Single-Speed mode (SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode (DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode (QSM) supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x (NOTE: QSM for the ADC is only supported in the IS, Left-Justified, Right-Justified interface formats. QSM for the DAC is supported in the IS, Left-Justified, Right-Justified and Time Division Multiplexed interface formats). All functions can be configured through software via a serial control port operable in SPI mode or in IC mode. Figure 1 on page 10 shows the recommended connections for the CS42448. See section "Register Description" on page 44 for the default register settings and options.
4.2
Analog Inputs 4.2.1 Line Level Inputs
AINx+ and AINx- are the line level differential analog inputs internally biased to VQ, approximately VA/2. Figure 10 on page 27 shows the full-scale analog input levels. The CS42448 also accommodates single-ended signals on all inputs, AIN1-AIN6. See "ADC Input Filter" on page 56 for the recommended input filters. For single-ended operation on ADC1-ADC3 (AIN1 to AIN6), the ADCx_SINGLE bit in the register "ADC Control & DAC De-emphasis (address 05h)" on page 49 must be set appropriately (see Figure 27 on page 56 for required external components). The gain/attenuation of the signal can be adjusted for each AINx independently through the "AINX Volume Control (address 11h-16h)" on page 53.
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The ADC output data is in 2's complement binary format. For inputs above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC Overflow bit in the register "Status (address 19h) (Read Only)" on page 54 to be set to a `1'.
5.0 V
3.9 V 2.5 V 1.1 V
VA AINx+
3.9 V 2.5 V 1.1 V
AINx-
Full-Scale Differential Input Level = (AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS
Figure 10. Full-Scale Input
4.2.2 ADC3 Analog Input
ADC3 accommodates differential as well as single-ended inputs. In Single-Ended mode, an internal MUX selects from up to 4 single-ended inputs.
AIN5A
Single-Ended Input Filter
ADC3
AIN5_MUX ADC3 SINGLE
AIN5B
Single-Ended Input Filter
1 0 1 58
AIN5+/-
0
Differential Input Filter
+ AIN5 -
57
0
VQ
1
AIN6_MUX
1 0 1 60 AIN6+/0
Differential Input Filter
+ AIN6 -
59
0
VQ
AIN6A
1
Single-Ended Input Filter
AIN6B
Single-Ended Input Filter
Figure 11. ADC3 Input Topology
Single-Ended mode is selected using the ADC3_SINGLE bit. Analog input selection is then made via the AINx_MUX bits. See register "ADC Control & DAC De-emphasis (address 05h)"
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on page 49 for all bit selections. Refer to Figure 11 on page 27 for the internal ADC3 analog input topology.
4.2.3 High Pass Filter and DC Offset Calibration
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the high pass filter is disabled during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS42448 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. The high pass filter for ADC1/ADC2 can be enabled and disabled. The high pass filter for ADC3 can be independently enabled and disabled. The high pass filters are controlled using the HPF_FREEZE bit in the register "ADC Control & DAC De-emphasis (address 05h)" on page 49.
4.3
Analog Outputs 4.3.1 Initialization
The initialization and Power-Down sequence flow chart is shown in Figure 12 on page 29. The CS42448 enters a Power-Down state upon initial power-up. The interpolation & decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down state until the RST pin is brought high. The control port is accessible once RST is high and the desired register settings can be loaded per the interface descriptions in the "Control Port Description and Timing" on page 38. Once MCLK is valid, VQ will ramp up to VA/2, and the internal voltage references, FILT+_ADC and FILT+_DAC, will begin powering up to normal operation. Power is applied to the D/A converters and switched-capacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. After an approximate 2000 sample period delay, normal operation begins.
4.3.2 Output Transient Control
The CS42448 uses Popguard(R) technology to minimize the effects of output transients during power-up and power-down. This technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to understand its operation. See "Popguard(R)" on page 30 for details. A Mute Control pin is also available for use with an optional mute circuit to mask output transients on the analog outputs. See "Mute Control" on page 30 for details. When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present on DAC_SDINx for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always be in a zero data state. If no zero audio is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it's zero data state.
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No Power 1. VQ = ? 2. Aout bias = ? 3. No audio signal generated.
PDN bit = '1'b?
Yes
Power-Down Mode 1. VQ = 0 V. 2. Aout bias = VQ. 3. No audio signal generated. 4. Control Port Registers retain settings.
No Power-Down (Power Applied) 1. VQ = 0 V. 2. Aout = VQ. 3. No audio signal generated. 4. Control Port Registers reset to default.
PopGuard(R)
Power-Up Ramp 1. VQ ramp up to VA/2. 2. Aout bias = VQ. 400 ms delay Power-Down Ramp 1. VQ ramp down to 0 V. 2. Aout bias = VQ. 250 ms delay
RST = Low?
Yes
No
Control Port Active Sub-Clocks Applied 1. LRCK valid. 2. SCLK valid. 3. Audio samples processed. No Control Port Access Detected? Yes
No Hardware Mode not supported. Codec will power up in an unknown state once all clocks and data are valid. It is recommended that the user setup up the codec via the control port before applying MCLK. Valid MCLK/LRCK Ratio? Yes
Software Mode Registers setup to desired settings.
No Power Transition 1. VQ = 0 V. 2. Aout bias = VQ. 3. Audible pops.
No Valid MCLK Applied? 2000 LRCK delay
Power-Down Transition 1. VQ = 0 V. 2. Aout bias = VQ. 3. Audible pops.
Yes
RST = Low ERROR: Power removed
Normal Operation 1. VQ = VA/2. 2. Aout bias = VQ. 3. Audio signal generated per register settings.
PDN bit set to '1'b
ERROR: MCLK/LRCK ratio change ERROR: MCLK removed
Analog Output Mute 1. VQ = VA/2. 2. Aout bias = VQ. 3. DAC outputs muted. 4. No audio signal generated.
Analog Output Freeze 1. VQ = VA/2. 2. Aout bias = VQ + last audio sample. 3. DAC Modulators stop operation. 4. Audible pops.
Figure 12. Audio Output Initialization Flow Chart
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4.3.3 Popguard(R) 4.3.3a Power-up
When the device is initially powered-up, the audio outputs, AOUTxx, are clamped to VQ which is initially low. After the RST pin is brought high and MCLK is applied, the outputs begin to ramp with VQ towards the nominal quiescent voltage. This ramp takes approximately 400 ms to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Once valid DAC_LRCK, DAC_SCLK and DAC_SDINx are applied, audio output begins approximately 2000 sample periods later.
4.3.3b
Power-down
To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the power. In order to do this, the PDN bit in register "Power Control (address 02h)" on page 45 must be set to `1' for a period of about 250 ms before removing power. During this time, voltage on VQ and the audio outputs discharge gradually to AGND. If power is removed before this 250 ms time period has passed a transient will occur when the VA supply drops below that of VQ. There is no minimum time for a power cycle. Power may be re-applied at any time.
4.3.4 Mute Control
The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The use of external mute circuits is not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops. MUTEC is in high impedance mode during power up or when the CS42448 is in power down mode by setting the PDN bit in the register "Power Control (address 02h)" on page 45 to a `1'. Once out of power-down mode the pin can be controlled by the user via the control port (see "MUTEC Pin Control (address 1Bh)" on page 55), or automatically asserted to the active state when zero data is present on all DAC inputs, when all DAC outputs are muted or when serial port clock errors occur. To prevent large transients on the output, it is recommended to mute the DAC outputs before the Mute Control pin is asserted.
4.3.5 Line-level Outputs and Filtering
The CS42448 contains on-chip buffer amplifiers capable of producing line level differential as well as single-ended outputs on AOUT1-AOUT8. These amplifiers are biased to a quiescent DC level of approximately VQ. The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low pass filter. See "DAC Output Filter" on page 59 for recommended output filter. The active filter configuration accounts for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins. Also shown is a passive filter configuration which minimizes costs and the number of components. Figure 13 shows the full-scale analog output levels. All outputs are internally biased to VQ, approximately VA/2.
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5.0 V
VA AOUTx+
2.5 V
4.125 V
0.875 V
4.125 V
AOUTx-
2.5 V 0.875 V
Full-Scale Differential Output Level = (AOUTx+) - (AOUTx-) = 6.5 VPP = 2.3 VRMS
Figure 13. Full-Scale Output
4.3.6 Digital Volume Control
Each DAC's output level is controlled via the Volume Control registers operating over the range of 0 to -127.5 dB attenuation with 0.5 dB resolution. See "AOUTX Volume Control (addresses 08h- 0Fh)" on page 52. Volume control changes are programmable to ramp in increments of 0.125 dB at the rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See "Transition Control (address 06h)" on page 50. Each output can be independently muted via mute control bits in the register "DAC Channel Mute (address 07h)" on page 52. When enabled, each AOUTx_MUTE bit attenuates the corresponding DAC to its maximum value (-127.5 dB). When the AOUTx_MUTE bit is disabled, the corresponding DAC returns to the attenuation level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by the SZC[1:0] bits.
4.3.7 De-Emphasis Filter
The CS42448 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 14. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single Speed Mode. Please see "DAC De-Emphasis Control (DAC_DEM)" on page 49 for de-emphasis control.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 14. De-Emphasis Curve
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4.4
System Clocking
The CODEC (ADC & DAC) serial audio interface ports operate both as a slave or master. The serial ports accept externally generated clocks in slave mode and will generate synchronous clocks derived from an input master clock in master mode. In the TDM format the ADC and DAC serial ports will only operate as a slave. In OLM #2 the serial ports will accept or output a 256Fs SCLK. See the registers "DAC Functional Mode (DAC_FM[1:0])" on page 46 and "ADC Functional Mode (ADC_FM[1:0])" on page 46 for setting up master/slave mode. The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must be an integer multiple of, and synchronous with, the system sample rate, Fs. The required integer ratios, along with some common frequencies, are illustrated in tables 2 to 4. The frequency range of MCLK must be specified using the MFREQ bits in register "MCLK Frequency (MFreq[2:0])" on page 46.
Sample Rate (kHz) 32 44.1 48
256x 8.1920 11.2896 12.2880
384x 12.2880 16.9344 18.4320
MCLK (MHz) 512x 16.3840 22.5792 24.5760
768x 24.5760 33.8688 36.8640
1024x 32.7680 45.1584 49.1520
Table 2. Single-Speed Mode Common Frequencies Sample Rate (kHz) 64 88.2 96 MCLK (MHz) 256x 16.3840 22.5792 24.5760
128x 8.1920 11.2896 12.2880
192x 12.2880 16.9344 18.4320
384x 24.5760 33.8688 36.8640
512x 32.7680 45.1584 49.1520
Table 3. Double-Speed Mode Common Frequencies Sample Rate (kHz) 176.4 192 MCLK (MHz) 128x 22.5792 24.5760
64x 11.2896 12.2880
96x 16.9344 18.4320
192x 33.8688 36.8640
256x 45.1584 49.1520
Table 4. Quad-Speed Mode Common Frequencies
4.5
CODEC Digital Interface Formats
The ADC and DAC serial ports support the IS, Left-Justified, Right-Justified, One-Line Mode (OLM) and TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figures 15-20. Data is clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. The serial bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronously derived from the master clock and be equal to 256x, 128x, 64x, 48x or 32x Fs depending on the interface format selected and desired speed mode. One Line Mode #1 and One Line Mode #2 will operate in master or slave mode. Refer to Table 5 for required clock ratios. The SCLK to sample rate (LRCK) ratios are shown in Tables 5 - 8.
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IS, Left-Justified, Right-Justified Ratio MCLK/LRCK SCLK/LRCK (Slave Mode) SCLK/LRCK (Master Mode) SSM DSM QSM 64x, 96x, 128x, 192x, 256x 32x, 48x, 64x 64x 256x, 384x, 512x, 128x, 192x, 256x, 768x, 1024x 384x, 512x 32x, 48x, 64x 64x 32x, 48x, 64x 64x
Table 5. IS, LJ, RJ Clock Ratios
OLM #1 SSM MCLK/LRCK SCLK/LRCK (Slave Mode) SCLK/LRCK (Master Mode) DSM QSM N/A N/A N/A 256x, 384x, 512x, 256x, 384x, 512x 768x, 1024x 128x 128x 128x 128x
Table 6. OLM#1 Clock Ratios
OLM #2 SSM MCLK/LRCK SCLK/LRCK (Slave Mode) SCLK/LRCK (Master Mode) DSM QSM N/A N/A N/A 256x, 384x, 512x, 256x, 384x, 512x 768x, 1024x 256x 256x 256x 256x
Table 7. OLM#2 Clock Ratios
TDM SSM MCLK/LRCK SCLK/LRCK (Slave Mode) SCLK/LRCK (Master Mode) DSM QSM (DAC only) 256x 256X N/A 256x, 384x, 512x, 256x, 384x, 512x 768x, 1024x 256X N/A 256X N/A
Table 8. TDM Clock Ratios
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33
4.5.1 IS
ADC/DAC_LRCK ADC/DAC_SCLK DAC_SDINx ADC_SDOUTx
MSB AOUT 1, 3, 5 or 7 AIN 1, 3, or 5 LS B M SB AOUT 2, 4, 6 or 8 AIN 2, 4, or 6 LS B L eft C h a n n el Rig ht C h a n n el
MSB
Figure 15. IS Format
4.5.2 Left-Justified
ADC/DAC_LRCK ADC/DAC_SCLK DAC_SDINx ADC_SDOUTx
MSB AOUT 1, 3, 5 or 7 AIN 1, 3, or 5 LS B M SB AOUT 2, 4, 6 or 8 AIN 2, 4, or 6 LS B L eft C h a n n el Rig ht C h a n n el
MSB
Figure 16. Left Justified Format
4.5.3 Right Justified
ADC/DAC_LRCK ADC/DAC_SCLK DAC_SDINx ADC_SDOUTx
M SB AOUT 1, 3, 5 or 7 AIN 1, 3, or 5 LSB MSB AOUT 2, 4, 6 or 8 AIN 2, 4, or 6 LSB L eft C h a n n el R ig ht C h a n n el
Figure 17. Right Justified Format
4.5.4 OLM #1
OLM #1 serial audio interface format operates in single or double-speed mode only and will master or slave ADC/DAC_SCLK at 128 Fs.
64 clks ADC/DAC_LRCK ADC/DAC_SCLK DAC_SDIN1 MSB LSB MSB AOUT3 20 clks LSB MSB AOUT5 20 clks LSB MSB LSB MSB AOUT2 20 clks AOUT8 20 clks AIN3 20 clks AIN5 20 clks AIN2 20 clks AIN4 20 clks AIN6 20 clks AOUT4 20 clks LSB MSB LSB MSB AOUT1 20 clks AOUT7 DAC_SDIN4 20 clks AIN1 64 clks
Left Channel
Right Channel
AOUT6 20 clks
ADC_SDOUT1
20 clks
Figure 18. One Line Mode #1 Format
34
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4.5.5 OLM #2
OLM #2 serial audio interface format operates in single or double-speed mode and will master or slave ADC/DAC_SCLK at 256Fs.
128 clks ADC/DAC_LRCK ADC/DAC_SCLK DAC_SDIN1 MSB AOUT1 24 clks AOUT7 DAC_SDIN4 24 clks AIN1 AIN3 24 clks AIN5 24 clks LSB MSB AOUT3 24 clks LSB MSB AOUT5 24 clks LSB MSB LSB MSB AOUT2 24 clks AOUT8 24 clks AIN2 24 clks AIN4 24 clks AIN6 24 clks AOUT4 24 clks LSB MSB LSB MSB 128 clks
Left Channel
Right Channel
AOUT6 24 clks
ADC_SDOUT1
24 clks
Figure 19. One Line Mode #2 Format
4.5.6 TDM
Data is received most significant bit (MSB) first, on the second rising edge of the DAC_SCLK occurring after a DAC_LRCK rising edge. All data is valid on the rising edge of DAC_SCLK. The AIN1 MSB is transmitted early but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted on the falling edge of ADC_SCLK. Each time slot is 32 bits wide, with the valid data sample left justified within the time slot. Valid data lengths are 16, 18, 20, or 24. ADC/DAC_SCLK must operate at 256Fs. ADC/DAC_LRCK identifies the start of a new frame and is equal to the sample rate, Fs. ADC/DAC_LRCK is sampled as valid on the rising ADC/DAC_SCLK edge preceding the most significant bit of the first data sample and must be held valid for at least 1 ADC/DAC_SCLK period. NOTE: The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode.
ADC/DAC_LRCK ADC/DAC_SCLK LSB MSB LSB MSB LSB MSB AOUT2 LSB MSB AOUT3 LSB MSB AOUT4 LSB MSB LSB MSB LSB MSB LSB MSB Bit or Word Wide 256 clks
DAC_SDIN1
AOUT1 32 clks ADC_SDOUT1 MSB AIN1 32 clks
AOUT5
AOUT6
AOUT7
AOUT8
32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB AIN2 32 clks AIN3 32 clks AIN4 32 clks AIN5 32 clks AIN6 32 clks AUX1 32 clks AUX2 32 clks
Figure 20. TDM Format
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35
4.5.7 I/O Channel Allocation
Digital Input/Output DAC_SDIN1 Interface Format IS, LJ, RJ OLM TDM IS, LJ, RJ OLM TDM IS, LJ, RJ OLM TDM IS, LJ, RJ OLM TDM IS, LJ, RJ OLM TDM IS, LJ, RJ OLM TDM IS, LJ, RJ OLM TDM Analog Output/Input Channel Allocation from/to Digital I/O AOUT 1,2 AOUT 1,2,3,4,5,6 AOUT 1,2,3,4,5,6,7,8 AOUT 3,4 Not Used Not Used AOUT 5,6 Not Used Not Used AOUT 7,8 AOUT 7,8 Not Used AIN 1,2 AIN 1,2,3,4,5,6 AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN) AIN 3,4 Not Used Not Used AIN 5,6 Not Used Not Used
DAC_SDIN2
DAC_SDIN3
DAC_SDIN4
ADC_SDOUT1
ADC_SDOUT2
ADC_SDOUT3
Table 9. Serial Audio Interface Channel Allocations
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4.6
AUX Port Digital Interface Formats
These serial data lines are used when supporting the TDM Mode of operation with an external ADC or S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate at 64xFs, where Fs is equal to the ADC sample rate (ADC_LRCK). If the AUX_SDIN signal is not being used, it should be tied to AGND via a pull-down resistor. The AUX port will operate in either the Left Justified or IS digital interface format with bit depths ranging from 16 to 24 bits. Settings for the AUX port are made through the register "Interface Formats (address 04h)" on page 47.
4.6.1 IS
AUX_LRCK AUX_SCLK AUX_SDIN
MSB AUX1 LS B M SB AUX2 LS B L eft C h a n n el R ig ht C h a n n el
MSB
Figure 21. AUX IS Format
4.6.2 Left Justified
AUX_LRCK AUX_SCLK AUX_SDIN
MSB AUX1 LS B M SB AUX2 LS B L e ft C h a n n el R ig ht C h a n n el
MSB
Figure 22. AUX Left Justified Format
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37
4.7
Control Port Description and Timing
The control port is used to access the registers allowing the CS42448 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and IC, with the CS42448 acting as a slave device. SPI mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. IC mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state.
4.7.1 SPI Mode
In SPI mode, CS is the CS42448 chip select signal, CCLK is the control port bit clock (input into the CS42448 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 23 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired. There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the adCS
CC LK C H IP ADDRESS C D IN 1001111 R/W C H IP ADDRESS LSB b y te n MSB LSB MSB LSB
MAP MSB
DATA
1001111
R/W
b y te 1 High Impedance CDOUT
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 23. Control Port Timing in SPI Mode
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DS648PP2
dressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecutively.
4.7.2 I2C Mode
In IC mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS42448 is being reset. The signal timings for a read and write cycle are shown in Figure 24 and Figure 25. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42448 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10010. To communicate with a CS42448, the chip address field, which is the first byte sent to the CS42448, should match 10010 followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS42448 after each input byte is read, and is input to the CS42448 from the microcontroller after each transmitted byte.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
START
1
0
0
1
0 AD1 AD0 0
6
5
4
3
ACK
ACK
ACK
ACK STOP
Figure 24. Control Port Timing, IC Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 0 AD1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
0 AD1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 25. Control Port Timing, IC Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 25, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 10010xx0 (chip address & write operation). Receive acknowledge bit.
DS648PP2 39
Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10010xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
4.8
Interrupts
The CS42448 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may be configured as an active low or active high CMOS driver or an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with multiple peripherals connected to the microcontroller interrupt input pin. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See "Status (address 19h) (Read Only)" on page 54. Each source may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the system designer.
4.9
Recommended Power-up Sequence
1) Hold RST low until the power supply is stable. In this state, the control port is reset to its default settings and VQ will remain low. 2) Bring RST high. The device will initially be in a low power state with VQ low. All features will default as described in the "Register Quick Reference" on page 42. 3) Perform a write operation to the Power Control register ("Power Control (address 02h)" on page 45) to set bit 0 to a `1'b. This will place the device in a power down state. 4) Load the desired register settings while keeping the PDN bit set to `1'b. 5) Start MCLK to the appropriate frequency, as discussed in section 4.4 on page 32. The device will initiate the power up sequence. 6) Set the PDN bit in the power control register to `0'b. VQ will ramp to approximately VA/2 according to the Popguard(R) specification in section Note 4.3.3 on page 30. 7) Apply ADC/DAC_LRCK, ADC/DAC_SCLK and DAC_SDINx. Following approximately 2000 sample periods, the device is initialized and ready for normal operation.
4.10
Reset and Power-up
It is recommended that reset be activated if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RST pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the ADC/DAC_FILT+
40
DS648PP2
pins. A time delay of approximately 400 ms is required after applying power to the device or after exiting a reset state. During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
4.11
Power Supply, Grounding, and PCB layout
As with any high resolution converter, the CS42448 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42448 as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42448 to minimize inductance effects. All signals, especially clocks, should be kept away from the ADC/DAC_FILT+, VQ pins in order to avoid unwanted coupling into the modulators. The ADC/DAC_FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from ADC/DAC_FILT+ and AGND. The CDB42448 evaluation board demonstrates the optimum layout and power supply arrangements. For optimal heat dissipation from the package, it is recommended that the area directly under the part be filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the backside ground is also recommended.
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41
5 REGISTER QUICK REFERENCE
NOTE: The default value in all "Reserved" registers must be preserved.
Addr Function
01h 02h ID
p 44
7
Chip_ID3 0 PDN_ADC3 0 DAC_FM1 1 FREEZE 0
6
Chip_ID2 0 PDN_ADC2 0 DAC_FM0 1 AUX_DIF 0 ADC3_HPF FREEZE 0 DAC_SZC1 0 AOUT7 MUTE 0 AOUT1 VOL6 0 AOUT2 VOL6 0 AOUT3 VOL6 0 AOUT4 VOL6 0 AOUT5 VOL6 0 AOUT6 VOL6 0 AOUT7 VOL6 0 AOUT8 VOL6 0 INV_AOUT7 0
5
Chip_ID1 0 PDN_ADC1 0 ADC_FM1 1 DAC_DIF2 1 DAC_DEM 0 DAC_SZC0 0 AOUT6 MUTE 0 AOUT1 VOL5 0 AOUT2 VOL5 0 AOUT3 VOL5 0 AOUT4 VOL5 0 AOUT5 VOL5 0 AOUT6 VOL5 0 AOUT7 VOL5 0 AOUT8 VOL5 0
4
Chip_ID0 1 PDN_DAC4 0 ADC_FM0 1 DAC_DIF1 1 ADC1 SINGLE 0 AMUTE 1 AOUT5 MUTE 0 AOUT1 VOL4 0 AOUT2 VOL4 0 AOUT3 VOL4 0 AOUT4 VOL4 0 AOUT5 VOL4 0 AOUT6 VOL4 0 AOUT7 VOL4 0 AOUT8 VOL4 0
3
Rev_ID3 0 PDN_DAC3 0 MFreq2 0 DAC_DIF0 0 ADC2 SINGLE 0 MUTE ADC_SP 0 AOUT4 MUTE 0 AOUT1 VOL3 0 AOUT2 VOL3 0 AOUT3 VOL3 0 AOUT4 VOL3 0 AOUT5 VOL3 0 AOUT6 VOL3 0 AOUT7 VOL3 0 AOUT8 VOL3 0
2
Rev_ID2 0
1
Rev_ID1 0
0
Rev_ID0 1 PDN 0 Reserved 0 ADC_DIF0 0 AIN6_MUX 0 ADC_SZC0 0 AOUT1 MUTE 0 AOUT1 VOL0 0 AOUT2 VOL0 0 AOUT3 VOL0 0 AOUT4 VOL0 0 AOUT5 VOL0 0 AOUT6 VOL0 0 AOUT7 VOL0 0 AOUT8 VOL0 0 INV_AOUT1 0
default
Power Control p 45 default Functional Mode p 46 default Interface Formats p 47 default
PDN_DAC2 PDN_DAC1 0 MFreq1 0 ADC_DIF2 1 ADC3 SINGLE 0 ADC_SNG VOL 0 AOUT3 MUTE 0 AOUT1 VOL2 0 AOUT2 VOL2 0 AOUT3 VOL2 0 AOUT4 VOL2 0 AOUT5 VOL2 0 AOUT6 VOL2 0 AOUT7 VOL2 0 AOUT8 VOL2 0 0 MFreq0 0 ADC_DIF1 1 AIN5_MUX 0 ADC_SZC1 0 AOUT2 MUTE 0 AOUT1 VOL1 0 AOUT2 VOL1 0 AOUT3 VOL1 0 AOUT4 VOL1 0 AOUT5 VOL1 0 AOUT6 VOL1 0 AOUT7 VOL1 0 AOUT8 VOL1 0
03h
04h
05h
ADC Control ADC1-2_HPF FREEZE (w/DAC_DEM) p 49 default 0 Transition Control p 50 default Channel Mute
p 52
06h
DAC_SNG VOL 0 AOUT8 MUTE 0 AOUT1 VOL7 0 AOUT2 VOL7 0 AOUT3 VOL7 0 AOUT4 VOL7 0 AOUT5 VOL7 0 AOUT6 VOL7 0 AOUT7 VOL7 0 AOUT8 VOL7 0
07h
default
08h
Vol. Control AOUT1 p 52 default Vol. Control AOUT2 p 52 default Vol. Control AOUT3 p 52 default Vol. Control AOUT4 p 52 default Vol. Control AOUT5 p 52 default Vol. Control AOUT6 p 52 default Vol. Control AOUT7 p 52 default Vol. Control AOUT8 p 52 default
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
DAC Chan- INV_AOUT8 nel Invert p 53 default 0
INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 0 0 0 0 0
42
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Addr Function
11h Vol. Control AIN1 p 52 default Vol. Control AIN2 p 53 default Vol. Control AIN3 p 52 default Vol. Control AIN4 p 53 default Vol. Control AIN5 p 52 default Vol. Control AIN6 p 53 default ADC Channel Invert p 53 default Status Control p 54 default Status
p 54
7
AIN1 VOL7 0 AIN2 VOL7 0 AIN3 VOL7 0 AIN4 VOL7 0 AIN5 VOL7 0 AIN6 VOL7 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
6
AIN1 VOL6 0 AIN2 VOL6 0 AIN3 VOL6 0 AIN4 VOL6 0 AIN5 VOL6 0 AIN6 VOL6 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
5
AIN1 VOL5 0 AIN2 VOL5 0 AIN3 VOL5 0 AIN4 VOL5 0 AIN5 VOL5 0 AIN6 VOL5 0 INV_A6 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0
4
AIN1 VOL4 0 AIN2 VOL4 0 AIN3 VOL4 0 AIN4 VOL4 0 AIN5 VOL4 0 AIN6 VOL4 0 INV_A5 0 Reserved 0 DAC_CLK Error X DAC_CLK Error_M 0 Reserved 0
3
AIN1 VOL3 0 AIN2 VOL3 0 AIN3 VOL3 0 AIN4 VOL3 0 AIN5 VOL3 0 AIN6 VOL3 0 INV_A4 0 INT1 0 ADC_CLK Error X ADC_CLK Error_M 0 Reserved 0
2
AIN1 VOL2 0 AIN2 VOL2 0 AIN3 VOL2 0 AIN4 VOL2 0 AIN5 VOL2 0 AIN6 VOL2 0 INV_A3 0 INT0 0 ADC3 OVFL X ADC3 OVFL_M 0 Reserved 0
1
AIN1 VOL1 0 AIN2 VOL1 0 AIN3 VOL1 0 AIN4 VOL1 0 AIN5 VOL1 0 AIN6 VOL1 0 INV_A2 0 Reserved 0 ADC2 OVFL X ADC2 OVFL_M 0 MCPolarity 0
0
AIN1 VOL0 0 AIN2 VOL0 0 AIN3 VOL0 0 AIN4 VOL0 0 AIN5 VOL0 0 AIN6 VOL0 0 INV_A1 0 Reserved 0 ADC1 OVFL X ADC1 OVFL_M 0 MUTEC Active 0
12h
13h
14h
15h
16h
17h
18h
19h
default
1Ah
Status Mask
p 55
default
1Bh
MUTEC p 55 default
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6 REGISTER DESCRIPTION
All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description.
6.1
MEMORY ADDRESS POINTER (MAP)
Not a register
7
INCR
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
6.1.1
INCREMENT(INCR)
Default = 1 Function: Memory address pointer auto increment control 0 - MAP is not incremented automatically. 1 - Internal MAP is automatically incremented after each read or write. 6.1.2 MEMORY ADDRESS POINTER (MAP[6:0])
Default = 0000001 Function: Memory address pointer (MAP). Sets the register address that will be read or written by the control port.
6.2
CHIP I.D. AND REVISION REGISTER (ADDRESS 01H) (READ ONLY)
6 Chip_ID2 5 Chip_ID1 4 Chip_ID0 3 Rev_ID3 2 Rev_ID2 1 Rev_ID1 0 Rev_ID0
7 Chip_ID3
6.2.1
CHIP I.D. (CHIP_ID[3:0])
Default = 0001 Function: I.D. code for the CS42448. Permanently set to 0001. 6.2.2 CHIP REVISION (REV_ID[3:0])
Default = 0001 Function: CS42448 revision level. Revision A is coded as 0001.
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6.3
7
POWER CONTROL (ADDRESS 02H)
6
PDN_ADC2
5
PDN_ADC1
4
PDN_DAC4
3
PDN_DAC3
2
PDN_DAC2
1
PDN_DAC1
0
PDN
PDN_ADC3
6.3.1
POWER DOWN ADC PAIRS(PDN_ADCX)
Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective ADC channel pair (ADC1 - AIN1/AIN2; ADC2 - AIN3/AIN4; and ADC3 - AIN5/AIN6) will remain in a reset state. 6.3.2 POWER DOWN DAC PAIRS (PDN_DACX)
Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4; DAC3 - AOUT5/AOUT6; and DAC4 - AOUT7/AOUT8) will remain in a reset state. It is advised that any change of these bits be made while the DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility of audible artifacts. 6.3.3 POWER DOWN (PDN)
Default = 0 0 - Disable 1 - Enable Function: The entire device will enter a low-power state when this function is enabled. The contents of the control registers are retained in this mode.
DS648PP2
45
6.4
7
FUNCTIONAL MODE (ADDRESS 03H)
6
DAC_FM0
5
ADC_FM1
4
ADC_FM0
3
MFreq2
2
MFreq1
1
MFreq0
0
Reserved
DAC_FM1
6.4.1
DAC FUNCTIONAL MODE (DAC_FM[1:0])
Default = 11 Master Mode 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) Slave Mode 11 - (Auto-detect sample rates) Function: Selects the required range of sample rates for the DAC serial port. 6.4.2 ADC FUNCTIONAL MODE (ADC_FM[1:0])
Default = 11 Master Mode 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) Slave Mode 11 - (Auto-detect sample rates) Function: Selects the required range of sample rates for the ADC serial port. 6.4.3 MCLK FREQUENCY (MFREQ[2:0])
Default = 000 Function: Sets the appropriate frequency for the supplied MCLK. For TDM and OLM #2 operation, ADC/DAC_SCLK must equal 256Fs. For OLM #1 operation, ADC/DAC_SCLK must equal 128Fs. MCLK can be equal to or greater than the higher frequency of ADC_SCLK or DAC_SCLK. Ratio (xFs) DSM QSM 128 64 192 96 256 128 384 192 512 256
MFreq2
0 0 0 0 1
MFreq1
0 0 1 1 X
MFreq0
0 1 0 1 X
Description 1.0290 MHz to 12.8000 MHz 1.5360 MHz to 19.2000 MHz 2.0480 MHz to 25.6000 MHz 3.0720 MHz to 38.4000 MHz 4.0960 MHz to 51.2000 MHz
SSM 256 384 512 768 1024
Table 10. MCLK Frequency Settings for IS, Left and Right Justified Interface Formats
46
DS648PP2
MFreq2
0 0 0 0 1
MFreq1
0 0 1 1 X
MFreq0
0 1 0 1 X
Description 1.0290 MHz to 12.8000 MHz 1.5360 MHz to 19.2000 MHz 2.0480 MHz to 25.6000 MHz 3.0720 MHz to 38.4000 MHz 4.0960 MHz to 51.2000 MHz
SSM 256 384 512 768 1024
Ratio (xFs) DSM QSM N/A N/A N/A N/A 256 N/A 384 N/A 512 256
Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats
6.5
7
INTERFACE FORMATS (ADDRESS 04H)
6
AUX_DIF
5
DAC_DIF2
4
DAC_DIF1
3
DAC_DIF0
2
ADC_DIF2
1
ADC_DIF1
0
ADC_DIF0
FREEZE
6.5.1
FREEZE CONTROLS (FREEZE)
Default = 0 Function: This function will freeze the previous settings of, and allow modifications to be made to the channel mutes, the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in these control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. 6.5.2 AUXILIARY DIGITAL INTERFACE FORMAT (AUX_DIF)
Default = 0 0 - Left Justified 1 - IS Function: This bit selects the digital interface format used for the AUX Serial Port. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 21-22. 6.5.3 DAC DIGITAL INTERFACE FORMAT (DAC_DIF[2:0])
Default = 110 Function: These bits select the digital interface format used for the DAC Serial Port. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section "CODEC Digital Interface Formats" on page 32. Refer to Table 9. "Serial Audio Interface Channel Allocations" on page 36.
DS648PP2
47
DAC_DIF2
0 0 0 0 1 1 1 1
DAC_DIF1
0 0 1 1 0 0 1 1
DAC_DIF0
0 1 0 1 0 1 0 1
Description Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 24-bit data Right Justified, 16-bit data One-Line #1, 20-bit One-Line #2, 24-bit TDM Mode, 24-bit (slave only) Reserved
Format
0 1 2 3 4 5 6 -
Figure
16 on page 34 15 on page 34 17 on page 34 17 on page 34 18 on page 34 19 on page 35 20 on page 35 -
Table 12. DAC Digital Interface Formats
6.5.4
ADC DIGITAL INTERFACE FORMAT (ADC_DIF[2:0])
Default = 110 Function: These bits select the digital interface format used for the ADC serial port. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section "CODEC Digital Interface Formats" on page 32. Refer to Table 9. "Serial Audio Interface Channel Allocations" on page 36. NOTE: The ADC does not meet Quad-Speed Mode timing specifications in the TDM interface format.
ADC_DIF2
0 0 0 0 1 1 1 1
ADC_DIF1
0 0 1 1 0 0 1 1
ADC_DIF0
0 1 0 1 0 1 0 1
Description Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 24-bit data Right Justified, 16-bit data One-Line #1, 20-bit One-Line #2, 24-bit TDM Mode, 24-bit (slave only) Reserved
Format
0 1 2 3 4 5 6 -
Figure
16 on page 34 15 on page 34 17 on page 34 17 on page 34 18 on page 34 19 on page 35 20 on page 35 -
Table 13. ADC Digital Interface Formats
48
DS648PP2
6.6
7
ADC CONTROL & DAC DE-EMPHASIS (ADDRESS 05H)
6
ADC3_HPF FREEZE
5
DAC_DEM
4
ADC1 SINGLE
3
ADC2 SINGLE
2
ADC3 SINGLE
1
AIN5_MUX
0
AIN6_MUX
ADC1-2_HPF FREEZE
6.6.1
ADC1-2 HIGH PASS FILTER FREEZE (ADC1-2_HPF FREEZE)
Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "ADC Digital Filter Characteristics" on page 14. 6.6.2 ADC3 HIGH PASS FILTER FREEZE (ADC3_HPF FREEZE)
Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "ADC Digital Filter Characteristics" on page 14. 6.6.3 DAC DE-EMPHASIS CONTROL (DAC_DEM)
Default = 0 0 - No De-Emphasis 1 - De-Emphasis Enabled (Auto-Detect Fs) Function: Enables the digital filter to maintain the standard 15s/50s digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless of this register setting, at any other sample rate. 6.6.4 ADC1 SINGLE-ENDED MODE (ADC1 SINGLE)
Default = 0 0 - Disabled; Differential input to ADC1 1 - Enabled; Single-Ended input to ADC1 Function: When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1. +6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be driven to the common mode of the ADC. See Figure 27 on page 56 for a graphical description. 6.6.5 ADC2 SINGLE-ENDED MODE (ADC2 SINGLE)
Default = 0 0 - Disabled; Differential input to ADC2 1 - Enabled; Single-Ended input to ADC2
DS648PP2
49
Function: When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2. +6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be driven to the common mode of the ADC. See Figure 27 on page 56 for a graphical description. 6.6.6 ADC3 SINGLE-ENDED MODE (ADC3 SINGLE)
Default = 0 0 - Disabled; Differential input to ADC 1 - Enabled; Single-Ended input to ADC Function: When disabled, this bit removes the 4:2 multiplexer from the signal path of ADC3 allowing a differential input. When enabled, this bit allows the user to choose between 4 single-ended inputs to ADC3, using the AIN5_MUX and AIN6_MUX bits. See Figure 11 on page 27 and Figure 27 on page 56 for graphical descriptions. 6.6.7 ANALOG INPUT CH. 5 MULTIPLEXER (AIN5_MUX)
Default = 0 0 - Single-Ended Input AIN5A 1 - Single-Ended Input AIN5B Function: ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX bit selects between two input channels (AIN5A or AIN5B) to be sent to ADC3 in single-ended mode. This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 27 for a graphical description. 6.6.8 ANALOG INPUT CH. 6 MULTIPLEXER (AIN6_MUX)
Default = 0 0 - Single-Ended Input AIN6A 1 - Single-Ended Input AIN6B Function: ADC3 can accept a single-ended input signal when the ADC3 SINGLE bit is enabled. The AIN6_MUX bit selects between two input channels (AIN6A or AIN6B) to be sent to ADC3 in single-ended mode. This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 27 for a graphical description.
6.7
7
TRANSITION CONTROL (ADDRESS 06H)
6
DAC_SZC1
5
DAC_SZC0
4
AMUTE
3
2
1
ADC_SZC1
0
ADC_SZC0
DAC_SNGVOL
MUTE ADC_SP ADC_SNGVOL
6.7.1
SINGLE VOLUME CONTROL (DAC_SNGVOL, ADC_SNGVOL)
Default = 0
50
DS648PP2
Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the AOUT1 and AIN1 Volume Control register and the other Volume Control registers are ignored. 6.7.2 SOFT RAMP AND ZERO CROSS CONTROL (ADC_SZC[1:0], DAC_SZC[1:0])
Default = 00 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected all volume level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 6.7.3 AUTO-MUTE (AMUTE)
Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converters of the CS42448 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the MUTEC pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).
DS648PP2
51
6.7.4
MUTE ADC SERIAL PORT (MUTE ADC_SP)
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, the ADC Serial Port will be muted.
6.8
7
DAC CHANNEL MUTE (ADDRESS 07H)
6
AOUT7_MUTE
5
AOUT6_MUTE
4
AOUT5_MUTE
3
AOUT4_MUTE
2
AOUT3_MUTE
1
AOUT2_MUTE
0
AOUT1_MUTE
AOUT8_MUTE
6.8.1
INDEPENDENT CHANNEL MUTE (AOUTX_MUTE)
Default = 0 0 - Disabled 1 - Enabled Function: The respective Digital-to-Analog converter outputs of the CS42448 will mute when enabled. The quiescent voltage on the outputs will be retained. The muting function is affected by the DAC Soft and Zero Cross bits (DAC_SZC[1:0]). When all channels are muted, the MUTEC pin will become active.
6.9
7
AOUTX VOLUME CONTROL (ADDRESSES 08H- 0FH)
6
AOUTx_VOL6
5
AOUTx_VOL5
4
AOUTx_VOL4
3
AOUTx_VOL3
2
AOUTx_VOL2
1
AOUTx_VOL1
0
AOUTx_VOL0
AOUTx_VOL7
6.9.1
VOLUME CONTROL (AOUTX_VOL[7:0])
Default = 00h Function: The AOUTx Volume Control registers allow independent setting of the signal levels in 0.5 dB increments from 0 dB to -127.5 dB. Volume settings are decoded as shown in Table 14. The volume changes are implemented as dictated by the Soft and Zero Cross bits (DAC_SZC[1:0]). All volume settings less than -127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the given channel.
Binary Code Volume Setting
00000000 00101000 01010000 01111000 10110100
0 dB -20 dB -40 dB -60 dB -90 dB
Table 14. Example AOUT Volume Settings
52
DS648PP2
6.10
7
DAC CHANNEL INVERT (ADDRESS 10H)
6
INV_AOUT7
5
INV_AOUT6
4
INV_AOUT5
3
INV_AOUT4
2
INV_AOUT3
1
INV_AOUT2
0
INV_AOUT1
INV_AOUT8
6.10.1 INVERT SIGNAL POLARITY (INV_AOUTX) Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels.
6.11
7
AINX VOLUME CONTROL (ADDRESS 11H-16H)
6
AINx_VOL6
5
AINx_VOL5
4
AINx_VOL4
3
AINx_VOL3
2
AINx_VOL2
1
AINx_VOL1
0
AINx_VOL0
AINx_VOL7
6.11.1 AINX VOLUME CONTROL (AINX_VOL[7:0]) Default = 00h Function: The level of AIN1 - AIN6 can be adjusted in 0.5 dB increments as dictated by the ADC Soft and Zero Cross bits (ADC_SZC[1:0]) from +24 to -64 dB. Levels are decoded in two's complement, as shown in Table 15.
Binary Code Volume Setting
0111 1111 *** 0011 0000 *** 0000 0000 1111 1111 1111 1110 *** 1000 0000
+24 dB *** +24 dB *** 0 dB -0.5 dB -1 dB *** -64 dB
Table 15. Example AIN Volume Settings
6.12
7
ADC CHANNEL INVERT (ADDRESS 17H)
6
Reserved
5
INV_AIN6
4
INV_AIN5
3
INV_AIN4
2
INV_AIN3
1
INV_AIN2
0
INV_AIN1
Reserved
6.12.1 INVERT SIGNAL POLARITY (INV_AINX) Default = 0 0 - Disabled 1 - Enabled
DS648PP2
53
Function: When enabled, these bits will invert the signal polarity of their respective channels.
6.13
7
STATUS CONTROL (ADDRESS 18H)
6
Reserved
5
Reserved
4
Reserved
3
INT1
2
INT0
1
Reserved
0
Reserved
Reserved
6.13.1 INTERRUPT PIN CONTROL (INT[1:0]) Default = 00 00 - Active high; high output indicates interrupt condition has occurred 01 - Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved Function: Determines how the Interrupt pin (INT) will indicate an interrupt condition. For DAC and ADC clock errors, the INT pin is set to "Level Active Mode" and will become active during the clock error. For the ADCx_OVFL error, the INT pin is set to Level Active Mode and will become active during the overflow error.
6.14
7
STATUS (ADDRESS 19H) (READ ONLY)
6
Reserved
5
Reserved
4
3
2
ADC3_OVFL
1
ADC2_OVFL
0
ADC1_OVFL
Reserved
DAC_CLK Error ADC_CLK Error
For all bits in this register, a "1" means the associated error condition has occurred at least once since the register was last read. A"0" means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always be "0" in this register. 6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR) Default = x Function: Indicates an invalid MCLK to DAC_LRCK ratio. This status flag is set to "Level Active Mode" and becomes active during the error condition. See "System Clocking" on page 32 for valid clock ratios. 6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR) Default = x Function: Indicates an invalid MCLK to ADC_LRCK ratio. This status flag is set to "Level Active Mode" and becomes active during the error condition. See "System Clocking" on page 32 for valid clock ratios.
54
DS648PP2
6.14.3 ADC OVERFLOW (ADCX_OVFL) Default = x Function: Indicates that there is an over-range condition anywhere in the CS42448 ADC signal path of each of the associated ADC's. These status flags become active on the arrival of the error condition.
6.15
7
STATUS MASK (ADDRESS 1AH)
6
Reserved
5
Reserved
4
DAC_CLK Error_M
3
ADC_CLK Error_M
2
1
0
Reserved
ADC3_OVFL_M ADC2_OVFL_M ADC1_OVFL_M
Default = 00000 Function: The bits of this register serve as a mask for the error sources found in the register "Status (address 19h) (Read Only)" on page 54. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Status register.
6.16
7
MUTEC PIN CONTROL (ADDRESS 1BH)
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
MCPolarity
0
MUTEC ACTIVE
Reserved
6.16.1 MUTEC POLARITY SELECT (MCPOLARITY) Default = 0 0 - Active low 1 - Active high Function: Determines the polarity of the MUTEC pin. 6.16.2 MUTE CONTROL ACTIVE (MUTEC ACTIVE) Default = 0 0 - MUTEC pin is not active. 1 - MUTEC pin is active. Function: The MUTEC pin will go high or low (depending on the MUTEC Polarity Select bit) when this bit is enabled.
DS648PP2
55
7 APPENDIX A: EXTERNAL FILTERS 7.1 ADC Input Filter
The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the digital passband frequency (n x 6.144 MHz), where n=0,1,2,... Refer to Figures 26 and 27 for a recommended analog input filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. Refer to Figures 28 and 29 for low cost, low component count passive input filters. The use of capacitors which have a large voltage coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity.
634 470 pF C0G 4.7 F + 634 91 634 470 pF C0G + 100 k 0.1 F 100 F 332 91 2700 pF C0G
ADC1-3 AINx+
100 k
VA
100 k
10 k
AINx-
Figure 26. Single to Differential Active Input Filter
634 VA 100 k 4.7 F 100 k 100 k 470 pF + 2700 pF C0G C0G
ADC1-2
91
AIN1+,2+,3+,4+
4.7 F
AIN1-,2-,3-,4-
634 VA 100 k 4.7 F 470 pF + 100 k 100 k 634 VA 100 k 4.7 F + 100 k 100 k 2700 pF C0G 470 pF C0G 91 2700 pF C0G C0G
ADC3
91
AIN5A,6A
AIN5B,6B
Figure 27. Single-Ended Active Input Filter
56
DS648PP2
7.1.1 Passive Input Filter
The passive filter implementation shown in Figure 28 will attenuate any noise energy at 6.144 MHz but will not provide optimum source impedance for the ADC modulators. Full analog performance will therefore not be realized using a passive filter. Figure 28 illustrates the unity gain, passive input filter solution. In this topology the distortion performance is affected, but the dynamic range performance is not limited.
150 10 F
ADC1-2 AIN1+,2+,3+,4+
100 k
2700 pF
C0G
AIN1-,2-,3-,44.7 F
150
10 F
ADC3 AIN5A,6A
100 k
2700 pF
C0G
150
10 F
AIN5B,6B
100 k 2700 pF
C0G
Figure 28. Passive Input Filter
7.1.2 Passive Input Filter w/Attenuation
Some applications may require signal attenuation prior to the ADC. The full-scale input voltage will scale with the analog power supply voltage. For VA = 5.0 V, the full-scale input voltage is approximately 2.8 Vpp, or 1 Vrms (most consumer audio line-level outputs range from 1.5 to 2 Vrms). Figure 29 shows a passive input filter with 6 dB of signal attenuation. Due to the relatively high input impedance on the analog inputs, the full distortion performance cannot be realized. Also, the resistor divider circuit will determine the input impedance into the input filter. In the circuit shown in Figure 29, the input impedance is approximately 5 k. By doubling the resistor values, the input impedance will increase to 10 k. However, in this case the distortion performance will drop due to the increase in series resistance on the analog inputs.
DS648PP2
57
2.5 k
10 F
ADC1-2 AIN1+,2+,3+,4+
2.5 k
2700 pF
C0G
AIN1-,2-,3-,44.7 F
2.5 k
10 F
ADC3 AIN5A,6A
2.5 k
2700 pF
C0G
2.5 k
10 F
AIN5B,6B
2.5 k 2700 pF
C0G
Figure 29. Passive Input Filter w/Attenuation
58
DS648PP2
7.2
DAC Output Filter
The CS42448 is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. Shown below is the recommended active and passive output filters.
1800 pF 4.75 k 390 pF 2.94 k + 1200 pF C0G 1.87 k 22 F C0G 22 F
DAC1-4 AOUTx AOUTx +
C0G 5.49 k
562 47.5 k
1.65 k 5600 pF C0G
887
Figure 30. Active Analog Output Filter
DAC1-4
3.3 F
AOUTx+
560
+ 10 k C R ext
C=
Figure 31. Passive Analog Output Filter
Rext+ 560 4FSRext560
DS648PP2
59
8 APPENDIX B: ADC FILTER PLOTS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0 -10 -20 -30
Amplitude (dB)
Amplitude (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 32. SSM Stopband Rejection
Figure 33. SSM Transition Band
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
-4 -5 -6 -7 -8 -9 -10 0.45
Amplitude (dB)
0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
-3
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 34. SSM Transition Band (Detail)
Figure 35. SSM Passband Ripple
0 -10 -20 -30 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -40
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
Amplitude (dB)
Frequency (normalized to Fs)
Figure 36. DSM Stopband Rejection
Figure 37. DSM Transition Band
60
DS648PP2
`
0 -1 -2
0 .10 0 .0 8 0 .0 6
Amplitude (dB)
-3 -4 -5 -6 -7 -8
Amplitude (dB)
0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -0 .0 8
-9 -10 0.46
-0 .10 0 .0 0
0.47 0.48 0.49 0.50 0.51 0.52
0 .0 5
0 .10
0 .15
0 .2 0
0 .2 5
0 .3 0
0 .3 5 0 .4 0
0 .4 5
0 .50
Frequency (normalized to Fs)
Fr e que ncy (norm alize d to Fs )
Figure 38. DSM Transition Band (Detail)
Figure 39. DSM Passband Ripple
Amplitude (dB)
-50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0
Amplitude (dB)
0 -10 -2 0 -3 0 -4 0
0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Fre que ncy (norm alize d to Fs )
Fre que ncy (norm alize d to Fs )
Figure 40. QSM Stopband Rejection
0 -1 -2
0 .10 0 .0 8 0 .0 6
Figure 41. QSM Transition Band
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.10
Amplitude (dB)
0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -0 .0 8 -0 .10 0 .0 0 0 .0 3 0 .0 5 0 .0 8 0 .10
Frequency (normalized to Fs)
0 .13
0 .15 0 .18 0 .2 0 0 .2 3 0 .2 5 0 .2 8
Fr e que ncy (norm alize d to Fs )
Figure 42. QSM Transition Band (Detail)
Figure 43. QSM Passband Ripple
DS648PP2
61
9 APPENDIX C: DAC FILTER PLOTS
Figure 44. SSM Stopband Rejection
Figure 45. SSM Transition Band
Figure 46. SSM Transition Band (detail)
Figure 47. SSM Passband Ripple
0 -10
-20
0 -10 -20 -30
-30 Amplitude dB
Amplitude dB
-40 -50 -60 -70 -80 -90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-40 -50 -60 -70 -80 -90
-100 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 48. DSM Stopband Rejection
Figure 49. DSM Transition Band
62
DS648PP2
0 -1 -2 -3 Amplitude dB
Amplitude dB
0.30 0.25 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15
-4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
-0.20 -0.25 -0.30 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 50. DSM Transition Band (detail)
Figure 51. DSM Passband Ripple
0
0
-10
-10
-20
-30
-20
-40 Amplitude (dB)
Amplitude (dB)
0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 1
-30
-50
-60
-40
-70
-50
-80
-90
-60
-100
0.35 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.75
Figure 52. QSM Stopband Rejection
Figure 53. QSM Transition Band
0 0.2 -5 0.15 -10 -15 -20 -25 -30 -35 -0.1 -40 -0.15 -45 -50 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 -0.2 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.1
Amplitude (dB)
0.05
Amplitude (dB)
0
-0.05
Figure 54. QSM Transition Band (detail)
Figure 55. QSM Passband Ripple
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10 PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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11 REFERENCES
1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html 2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 3) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997. 4) Cirrus Logic, A Stereo 16-bit delta-sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988. 5) Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 6) Cirrus Logic, An 18-Bit Dual-Channel Oversampling delta-sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 7) Cirrus Logic, How to Achieve Optimum Performance from delta-sigma A/D and D/A Converters,by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 8) Cirrus Logic, A Fifth-Order Delta-sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 9) Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com
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12 PACKAGE INFORMATION
64L LQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
MIN --0.002 0.007 0.461 0.390 0.461 0.390 0.016 0.018 0.000 * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026
DIM A A1 B D D1 E E1 e* L
INCHES NOM 0.55 0.004 0.008 0.472 BSC 0.393 BSC 0.472 BSC 0.393 BSC 0.020 BSC 0.024 4
MAX 0.063 0.006 0.011 0.484 0.398 0.484 0.398 0.024 0.030 7.000
MIN --0.05 0.17 11.70 9.90 11.70 9.90 0.40 0.45 0.00
MILLIMETERS NOM 1.40 0.10 0.20 12.0 BSC 10.0 BSC 12.0 BSC 10.0 BSC 0.50 BSC 0.60 4
MAX 1.60 0.15 0.27 12.30 10.10 12.30 10.10 0.60 0.75 7.00
12.1
Thermal Characteristics
Parameter Symbol
2 Layer Board 4 Layer Board
Min -
Typ 50 37
Max -
Units C/Watt C/Watt
Junction to Ambient Thermal Impedance
JA JA
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13 ORDERING INFORMATION
Product CS42448 Description Package Pb-Free YES Container Rail Commercial -10 to +70 C Tape & Reel Rail Automotive -40 to +85 C Tape & Reel Grade Temp Range Order # CS42448-CQZ CS42448-CQZR CS42448-DQZ CS42448-DQZR CDB42448
6-in, 8-out CODEC for Sur64L-LQFP round Sound Apps -
CDB42448 CS42448 Evaluation Board
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14 REVISION HISTORY
Revision A1 A2 PP1 Date July 2004 October 2004 January 2005 Initial Release Corrected IC Address in section 4.7.2 on page 39. Corrected Chip I.D. in section 6.2.1 on page 44. Initial Preliminary Product (PP) Release subject to legal notice below. Added pin numbers to "Typical Connection Diagram" on page 10. Changed ADC TDM, Double-Speed Mode parameters. See Note 2 on page 11 and Note 18 on page 21. Added ADC3 MUX Interchannel Isolation characteristic in section "Characteristics and Specifications" beginning on page 11. Changed SCLK Falling Edge to ADC_SDOUT Output Valid (tdpd) maximum specification to 35 ns in section "Characteristics and Specifications" beginning on page 11. Changed ADC Passband Ripple maximum specifications for SSM, DSM & QSM in section "Characteristics and Specifications" beginning on page 11. Changed DAC Frequency Response specifications for SSM, DSM & QSM in section "Characteristics and Specifications" beginning on page 11. Changed ADC Quad-Speed Mode parameters. See Note 19 on page 21. Added section "De-Emphasis Filter" on page 31. Added SCLK/LRCK & MCLK/LRCK ratio parameters in Tables 5 - 8 on page 33. Corrected section "TDM" on page 35. Changed AIN1-6 Volume Control range from (+12 dB to -115.5 dB) to (+24 dB to -64 dB) in register "AINx Volume Control (AINx_VOL[7:0])" on page 53. Removed the "Error Mode (MODE[1:0])" control bits from register "Status Control (address 18h)" on page 54. See "Interrupt Pin Control (INT[1:0])" on page 54, "ADC CLOCK ERROR (ADC_CLK Error)" on page 54 and "ADC Overflow (ADCX_OVFL)" on page 55 for the Active Mode setting. Corrected Figures 27-29. Added section "Ordering Information" on page 67.
Table 16. Revision History
Changes
PP2
February 2005
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Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard(R) are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a registered trademark of Motorola, Inc.
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